Logic Effort

$$\begin{gathered} D(gate)=\frac{ln2R_{eq,gate}(C_{int,gate}+C_L)}{ln2R_{eq,inv}{C}_{int,inv}}=\frac{R_{eq,gate}(C_{int,gate}+C_L)}{R_{eq,inv}{C}_{int,inv}} \\ =\frac{R_{eq,gate}{C}_{int,gate}}{R_{eq,inv}{C}_{int,inv}}+\frac{R_{eq,gate}{C}_L}{R_{eq,inv}{C}_{int,inv}} \\ =\frac{R_{eq,gate}{C}_{int,gate}}{R_{eq,inv}{C}_{int,inv}}+\frac{R_{eq,gate}{C}_{gin,gate}}{R_{eq,inv}{C}_{int,inv}}\ast \frac{C_L}{C_{gin,gate}}=P+LE\ast FO\text{P+LE∗FO}P+LE\ast FO \\ =Parasiticdelay(P)+LogicalEffort(LE)\ast Fanout(FO)\text{Parasiticdelay(P) + LogicalEffort(LE) ∗ Fanout(FO)}Parasiticdelay(P)+Lo \end{gathered}$$

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