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数字逻辑电路实验:基本电子时钟

最编程 2024-04-25 17:51:15
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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity seltime is port(clk:in std_logic; h,m,s:in std_logic_vector(7 downto 0); sel:out std_logic_vector(2 downto 0); seg:out std_logic_vector(6 downto 0)); end seltime; architecture beha of seltime is signal scan_count:std_logic_vector(2 downto 0); signal dat:std_logic_vector(3 downto 0); begin scan:process(clk) begin if clk'event and clk='1' then scan_count<=scan_count+1; end if; sel<=scan_count; case scan_count is when "111"=>dat<=s(3 downto 0); when "110"=>dat<=s(7 downto 4); when "101"=>dat<=m(3 downto 0); when "100"=>dat<=m(7 downto 4); when "011"=>dat<=h(3 downto 0); when "010"=>dat<=h(7 downto 4); when others=>NULL; end case; end process scan; decode:process(scan_count) begin case dat is when"0000"=>seg<="0111111"; when"0001"=>seg<="0000110"; when"0010"=>seg<="1011011"; when"0011"=>seg<="1001111"; when"0100"=>seg<="1100110"; when"0101"=>seg<="1101101"; when"0110"=>seg<="1111101"; when"0111"=>seg<="0000111"; when"1000"=>seg<="1111111"; when"1001"=>seg<="1101111"; when others=>seg<="1000000"; end case; end process decode; end beha;

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