ZYNQ MP AXI 数据转换 IP 使用流程说明
最编程
2024-05-01 22:51:10
...
`timescale 1ns/1ps
module Control_AXI_stream (
input i_clk ,
input i_rst_n ,
output [31:0] S_AXIS_S2MM_0_tdata ,
output [3:0] S_AXIS_S2MM_0_tkeep ,
output S_AXIS_S2MM_0_tlast ,
input S_AXIS_S2MM_0_tready ,
output S_AXIS_S2MM_0_tvalid ,
output [71:0] S_AXIS_S2MM_CMD_0_tdata ,
input S_AXIS_S2MM_CMD_0_tready ,
output S_AXIS_S2MM_CMD_0_tvalid
);
////传输起始控制
wire w_tri_en;
vio_0 inst_vio_0 (
.clk (i_clk),
.probe_out0 (w_tri_en),
.probe_out1 ()
);
reg [1:0] r_tri_en_edge = 'd0;
always @(posedge i_clk)
begin
r_tri_en_edge <= {r_tri_en_edge[0],w_tri_en};
end
////命令注入
reg [71:0] r_S_AXIS_S2MM_CMD_0_tdata = 'd0;
reg r_S_AXIS_S2MM_CMD_0_tvalid = 'd0;
always @(posedge i_clk)
begin
if (r_tri_en_edge == 2'b01)
r_S_AXIS_S2MM_CMD_0_tvalid <= 1'b1;
else if (S_AXIS_S2MM_CMD_0_tready)
r_S_AXIS_S2MM_CMD_0_tvalid <= 1'b0;
end
reg [31:0] r_addr_axi = 'd0;
reg r_S_AXIS_S2MM_0_tlast = 1'b0;
always @(posedge i_clk)
begin
if (r_S_AXIS_S2MM_0_tlast & S_AXIS_S2MM_0_tready)
begin
if (r_addr_axi == 'd192)
r_addr_axi <= 'd0;
else
r_addr_axi <= r_addr_axi + 'd64;
end
end
wire [71:0] w_S_AXIS_S2MM_CMD_0_tdata;
wire [63:32] w_SADDR;
wire [31:31] w_DRR;
wire [30:30] w_EOF;
wire [29:24] w_DSA;
wire [23:23] w_Type;
wire [22:0] w_BTT;
assign w_SADDR = r_addr_axi;
assign w_DRR = 'd0;
assign w_EOF = 'd1;
assign w_DSA = 'd0;
assign w_Type = 'd1;
assign w_BTT = 'd256; //256bytes
assign w_S_AXIS_S2MM_CMD_0_tdata = {
8'd0,
w_SADDR,
w_DRR,
w_EOF,
w_DSA,
w_Type,
w_BTT
};
reg [31:0] r_data = 'h1234;
reg r_S_AXIS_S2MM_0_tvalid = 1'b0;
always @(posedge i_clk)
begin
if (r_S_AXIS_S2MM_0_tvalid & S_AXIS_S2MM_0_tready)
r_data <= r_data + 'd1;
end
reg [5:0] r_cnt_num = 'd0;
always @(posedge i_clk)
begin
if (r_S_AXIS_S2MM_0_tvalid)
begin
if (S_AXIS_S2MM_0_tready)
r_cnt_num <= r_cnt_num + 'd1;
end
else
r_cnt_num <= 'd0;
end
always @(posedge i_clk)
begin
if ((r_cnt_num == 'd62) && S_AXIS_S2MM_0_tready)
r_S_AXIS_S2MM_0_tlast <= 1'b1;
else if (r_S_AXIS_S2MM_0_tlast & S_AXIS_S2MM_0_tready)
r_S_AXIS_S2MM_0_tlast <= 1'b0;
end
always @(posedge i_clk)
begin
if (S_AXIS_S2MM_CMD_0_tready & r_S_AXIS_S2MM_CMD_0_tvalid)
r_S_AXIS_S2MM_0_tvalid <= 1'b1;
else if (r_S_AXIS_S2MM_0_tlast & S_AXIS_S2MM_0_tready)
r_S_AXIS_S2MM_0_tvalid <= 1'b0;
end
assign S_AXIS_S2MM_0_tdata = r_data;
assign S_AXIS_S2MM_0_tkeep = 4'b1111;
assign S_AXIS_S2MM_0_tlast = r_S_AXIS_S2MM_0_tlast;
assign S_AXIS_S2MM_0_tvalid = r_S_AXIS_S2MM_0_tvalid;
assign S_AXIS_S2MM_CMD_0_tdata = w_S_AXIS_S2MM_CMD_0_tdata;
assign S_AXIS_S2MM_CMD_0_tvalid = r_S_AXIS_S2MM_CMD_0_tvalid;
////debug
ila_0 inst_ila_0 (
.clk (i_clk),
.probe0 (S_AXIS_S2MM_0_tdata),
.probe1 (S_AXIS_S2MM_0_tkeep),
.probe2 (S_AXIS_S2MM_0_tlast),
.probe3 (S_AXIS_S2MM_0_tready),
.probe4 (S_AXIS_S2MM_0_tvalid),
.probe5 (S_AXIS_S2MM_CMD_0_tdata),
.probe6 (S_AXIS_S2MM_CMD_0_tready),
.probe7 (S_AXIS_S2MM_CMD_0_tvalid),
.probe8 (r_addr_axi),
.probe9 (r_cnt_num)
);
////debug end
endmodule // end the Control_AXI_stream model